A New Logical Architecture of Wallace Tree Encoder, with Reduced Computations as well as Auto-detection of Bubble Error in Flash ADC

Abstract

Speed is the major bottleneck of any flash ADC (analog-to-digital converter), which arises out from the nature computation that one ADC has to undergo at its different phases. In flash ADC one major component is the conversion of thermometer code to binary code. With the increase of operating frequency, error may occur in thermal to binary conversion, which is termed as bubble error. A new logical structure is proposed herewith, which reduces the number of computations by 40% with inherent ability of auto-detection and compensation of 1st order bubble error as well a certain type of 2nd order bubble errors.

Keywords: flash ADC, bubble error correction, Wallace tree encoder, full adder, k-map

Cite this Article: Anirban Roy, Satish Kumar, K.L. Baishnab. A New Logical Architecture of Wallace Tree Encoder, with Reduced Computations as well as Auto-detection of Bubble Error in Flash ADC. International Journal of Wireless Network Security. 2019; 5(2): 1–14p.