Design of Low Power 9T SRAM Cell Using DG FINFET at Different Nanometer Regime

Ummul Qura Ansari, Dr. Kamal Prakash Pandey

Abstract


Abstract

According to this paper, we are represented 9T SRAMcells exploitassorted nanometer expertise. This paper compares the performance of 9T SRAM cell technologies, which include performance parameters such as the Average write delay and write power product delay, study manners of all SRAM cells are observed. Therefore, the 9TSRAMcells at 90nm technology constantly devourshort Average power; get betterstudysolidity as contrast to the 9T SRAM cells at 180nm technology. The objective of this paper is to diminish thelow power, develop the read behavior of the dissimilar SRAM cell formation applytempoimplement at 90nm and 180nm expertise. DG FINFET techniques have been employedto reduce the power consumed by the SRAM cell. The results show that the DG FINFET based SRAM cell is the best performerin terms of power consumption. This paper defines the utilize of Double Gate FINFET technology give low outflow and elevated performance operation by exploit maximum speed and short threshold voltage transistors for logic cell.

Key Words: CMOS, 9T SRAM cell, Low Power, Average write delay, write power product delay, Cadence.

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