Investigation of delay and power in 6-T SRAM cell at 90 nm Technology

Abstract

In present paper an implementation and analysis of 6T SRAM has been performed with optimized cell ratio and pull up ratio regarding with the delay and power consumption by using 90nm technology on standard cadence virtuoso and ADE tool. It has been observed that with increase in supply voltage from 500 mV to 1V a slight decrement in write delay at logic 0. Furthermore, read delay is approximately 5 times of write delay due to more swing occur in charging and discharging of bit-lines in read operation. It has been also found that as the temperature is increased delay also increases. At maximum value of temperature i.e. 100ᵒC the delay is maximum in write 0 value equals to 0.247 n sec and in write 1 value equals to 0.018nsec. It has been also inferred that as supply voltage is increased average power is increased. When Vdd is increased from 500mV to 1V, average power is increasing. At maximum Vdd i.e. 1V, value of average power is 35.20 nW.

Keywords: SRAM, read delay, write delay, power dissipation, transistor sizing.

Cite this Article: Neha Sharma, V. K. Tomar. Investigation of Delay and Power in 6-T SRAM Cell at 90 nm Technology. International Journal of Information Security and Software Engineering. 2020; 6(1): 18–24p.